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0V to 16V, Dual Hot-Swap Controller with 10-Bit
Current and Voltage Monitor and 4 LED Drivers
Table 1b. Register Address Map (General) (continued)
REGISTER
LED_Flash
LED_ph_pu
LED_state
DESCRIPTION
LED flash/GPIO enable register
LED phase/weak pullup enable register
LED pins voltage state register (LED pins set open)
ADDRESS
(HEX CODE)
0x43
0x44
0x45
RESET
VALUE
0x00
0x00
0x00
READ/
WRITE
R/W
R/W
R
Grouping Hot-Swap Channels
The MAX5970 can operate as either two independent
hot-swap controllers or as a pair. See Table 2 for the
configuration option based on the MODE logic level.
Hot-Swap Channels On-Off Control
Depending on the configuration of the Chx_EN1 and
Chx_EN2 bits, when V IN is above the V UVLO threshold
and the ON_ input reaches its internal threshold, the
MAX5970 turns on the external n-channel MOSFET for
the corresponding channel, allowing power to flow to the
load. The channel is enabled depending on the output of
a majority function. Chx_EN1, Chx_EN2, and ON_ are the
inputs to the majority function and the channel is enabled
when two or more of these inputs are 1.
Table 2. Grouping Hot-Swap Channels
(Channel enabled) = (Chx_EN1 x Chx_EN2) +
(Chx_EN1 x ON_) + (Chx_EN2 x ON_)
The inputs ON_ and Chx_EN2 can be set externally; the
initial state of the Chx_EN2 bits in register chxen is set
by the state of the HWEN input when V IN rises above
V UVLO . The ON_ inputs connect to internal precision
analog comparators with a 0.6V threshold. Whenever
V ON_ is above 0.6V, the corresponding ON_ bit in regis-
ter status1[0:1] is set to 1. The inputs Chx_EN1 and Chx_
EN2 can be set using the I 2 C interface; the Chx_EN1
bits have a default value of 0. This makes it possible to
enable or disable each of the MAX5970 channels inde-
pendently with or without using the I 2 C interface (see
Tables 3, 4a, and 4b).
MODE INPUT
Low
High/unconnected
FUNCTION
Independent
Paired
DESCRIPTION
Each channel operates as an independent hot-swap controller. A fault
shutdown in one channel does not affect operation of other channel.
Channel 0 and channel 1 operate together as one pair. A fault shutdown in
one channel shuts down both channels in the pair. Both channels share the
ADC monitoring capability.
Table 3. chxen Register Format
Description:
Register Title:
Register Address:
Channel enable bits, from HWEN input and Chx_EN1 bits
chxen
0x3B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
VALUE
Ch2_EN2
Ch2_EN1
Ch1_EN2
Ch1_EN1
—
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
14
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